The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor includes a gate electrode as a control electrode overlying a semiconductor substrate and spaced-apart source and drain regions in the substrate, between which a current can flow. A gate dielectric is disposed between the gate electrode and the semiconductor substrate to electrically isolate the gate electrode from the substrate. A control voltage applied to the gate electrode controls the flow of current through a channel in the substrate underlying the gate electrode between the source and drain regions.
The semiconductor industry is continuously moving toward the fabrication of smaller and more complex microelectronic components with higher performance. Memory cells are an important part of many microelectronic components, and smaller and more reliable memory cells are desirable. One type of memory cell uses flash memory that is non-volatile and re-writable. Non-volatile memory retains stored information even when the memory cell is de-powered, and stored information can be changed when a memory cell is re-writable. Some memory cells for flash memory store information by either charging or draining an electrically isolated component, such as a floating gate, and the information is recalled by determining if the isolated component is charged or not. Floating gate memory cells are typically provided with associated control gates and select gates that are utilized in the storage, retrieval, and erasing of memory on the floating gate.
Integrated circuits that include MOSFETs and flash memory cells are generally fabricated at facilities that include a series of discrete fabrication stages where specific operations are conducted to form various structures in the integrated circuits, including floating gate memory cells and associated control gates and select gates. After the facilities are constructed and the various fabrication stages are set up, modification of the fabrication stages is often difficult or impossible such that design changes for MOSFETs or flash memory cells cannot be implemented without retooling or addition of supplemental fabrication stages.
Fabrication of integrated circuits that include MOSFETs operating at various input/output (I/O) voltages is generally limited by the pre-existing fabrication stages at the fabrication facilities. For example, existing facilities that are set up to produce integrated circuits with 55 nm SST eFlash configurations are generally incapable of fabricating MOSFETs that operate at outside of original design I/O voltages for which the facilities were originally designed to fabricate, especially I/O voltages of greater than 3.3V. I/O voltages are generally dependent upon gate dielectric thickness, and facilities that are set up to produce integrated circuits with 55 nm SST eFlash configurations are generally not configured to produce MOSFETs with gate dielectric thicknesses sufficient to operate at I/O voltages in excess of 3.3V without adding supplemental fabrication stages to achieve sufficiently large gate dielectric thicknesses. However, it is to be appreciated that difficulties with fabricating MOSFETs that operate outside of original design I/O voltages (without adding supplemental fabrication stages) are not limited to 55 nm SST eFlash facilities.
Accordingly, it is desirable to provide integrated circuits and methods of forming integrated circuits including MOSFETs that operate at modified I/O voltages, especially higher I/O voltages than design I/O voltages for integrated circuits fabricated in the same fabrication stages, without adding supplemental fabrication stages. There is also a desire to develop methods for determining dielectric layer thickness in semiconductor devices. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.